MicroSRC: what −140 dBFS actually took
The measured numbers behind the sample-rate converter, and the parts of the design that earned them.
The headline number for MicroSRC is −140.6 dBFS THD+N at 997 Hz and −1 dBFS, measured through a fully digital loopback doing asynchronous 48 → 44.1 kHz conversion. That is a real measurement of the converter, not a spec sheet aspiration, and the loopback matters: there is no DAC or ADC in the path to hide behind or to blame.
The full set
| Metric | Measured |
|---|---|
| THD+N (997 Hz @ −1 dBFS) | −140.6 dBFS |
| Worst discrete spur | −158 dBFS |
| Intermodulation (CCIF 19 + 20 kHz) | −158 dBFS |
| Dynamic range (A-weighted) | 142.8 dB |
| Low-level linearity (−60 dBFS) | 0.000 dB error |
| Multitone (31 tones) | no artifact above −181 dBFS |
| Frequency response (100 Hz – 20 kHz) | flat within ±0.02 dB |
| Phase | linear (constant group delay) |
The frequency response line is the one I am quietest about and proudest of. Plenty of converters are flat on paper and then droop a fraction of a decibel approaching 20 kHz because the interpolation filter is cheaper than it looks. ±0.02 dB with no droop means the filter is doing its job all the way out.
Why both ports are slaves
The whole reason MicroSRC exists is that two devices which each insist on being clock master cannot be wired together. If MicroSRC solved that by becoming a master itself, it would just be a third device with an opinion about the clock.
So it never drives an audio clock. The source drives the input port’s BCK and LRCK; the sink drives the output port’s. MicroSRC lives entirely in between, tracking both, converting continuously. Rate changes on either side get detected and handled without anyone being told.
That constraint is what makes the servo interesting, and it is most of where the engineering time went.